1. Technical Field
The present invention relates to an oscillator circuit, and, particularly, to an oscillator circuit formed on a semiconductor integrated circuit and connected to a resonant circuit including a crystal unit, a ceramic resonator, an LC circuit and the like.
2. Related Art
According to the related art, an oscillator circuit formed on a semiconductor integrated circuit while being connected to a crystal unit so as to exhibit an oscillation has been used (see, for example, Japanese Patent Application Laid-Open (JP-A) NO. 2005-303639). In such an oscillator circuit, in order to lower a supply voltage and obtain a wide range and low current consumption when a battery is used, there has been proposed an oscillator circuit using a PTAT (Proportional Absolute Temperature) current source, which uses a reference current such as a bandgap current, and an inverter type oscillating buffer.
As the oscillator circuit according to the related art, in order to obtain an oscillation gain with a required magnitude under the low supply voltage, an oscillating inverting amplifier has been designed with a core transistor.
In a core transistor (for example, with a supply voltage of 1.8 V), as compared with an I/O (Input/Output) transistor (for example, with a supply voltage of 3.3 V) constituting an I/O circuit, it is typical for the thickness of a gate oxide layer to be thin and the breakdown voltage to be low. As compared with the I/O transistor, the core transistor can allow a desired current to flow at a lower voltage by the magnitude relation of the gate oxide layer. Thus, an oscillation gain with a desired magnitude can be ensured at a low supply voltage. That is, applying core transistor to this circuit is more adapted to low power consumption as compared with applying I/O transistor.
FIG. 12 shows one example of such an oscillator circuit. As shown in FIG. 12, the oscillator circuit 100 includes a PTAT current source 12, an oscillating buffer 14, an NMOS transistor 16, a feedback resistor Rf, switch devices 20A and 20B and an output buffer 22.
The PTAT current source 12 includes a bias current generating circuit 28, a current mirror circuit 38 and a PMOS transistor 40. The bias current generating circuit 28 includes a PMOS transistor 24, and a bandgap current source 26 provided with a diode and a bipolar device. The current mirror circuit 38 includes PMOS transistors 30 and 32 and NMOS transistors 34 and 36.
The oscillating buffer 14 includes a CMOS inverter formed by a PMOS transistor 42 and an NMOS transistor 44. A source of the PMOS transistor 42 is connected to a drain of the PMOS transistor 40. A source of the NMOS transistor 44 is connected to a drain of the NMOS transistor 16. A source of the NMOS transistor 16 is grounded. A gate of the NMOS transistor 16 is connected to an enable terminal EB.
The feedback resistor Rf is connected in parallel to the oscillating buffer 14. The switch device 20A is connected between one end of the feedback resistor Rf and an input side of the oscillating buffer 14. The switch device 20B is connected between the other end of the feedback resistor Rf and an output side of the oscillating buffer 14.
The switch devices 20A and 20B, for example, each include an NMOS transistor, and have gates connected to a feedback resistor enable terminal EBFBR. Further, the switch devices 20A and 20B may use a transfer gate including a PMOS transistor and an NMOS transistor.
The input side of the oscillating buffer 14, that is, the gates of the PMOS transistor 42 and the NMOS transistor 44 are connected to an input terminal XI. The output side of the oscillating buffer 14, that is, the drains of the PMOS transistor 42 and the NMOS transistor 44 are connected to an output terminal XO and an input terminal of the output buffer 22.
A resonant circuit 46 is connected to the input terminal XI and the output terminal XO. The resonant circuit 46 includes a crystal unit Xtal, external capacitors Cg and Cd, and a dumping resistor Rd. The dumping resistor Rd is provided to adjust a resistance value, thereby reducing the probability that the crystal unit Xtal will break when a level of drive (power from a current Id flowing when the external capacitor Cd is charged) of the oscillator circuit is higher than the power designated by the crystal unit Xtal.
Hereinafter, a typical oscillating operation of the oscillator circuit 100 will be described.
When the oscillator circuit starts to oscillate, as shown in FIG. 13, a control signal input to the feedback resistor enable terminal EBFBR is changed from a low level (hereinafter, referred to an L level) to a high level (hereinafter, referred to an H level) and a control signal input to the enable terminal EB is changed from an L level to an H level, so that the PTAT current source 12 starts to operate.
Thus, the NMOS transistor 16 is turned on and the switch devices 20A and 20B are turned on. The PTAT current source 12 allows a bias current Ibg generated by the bias current generating circuit 28 and a current Iall set by the current mirror circuit 38 to flow.
Thereafter, voltage levels of each node (terminal) are changed as follows. First, when the voltage level of the output terminal XO in its initial state is 0 [V] level, the current Iall flows toward the external capacitor Cd from the PTAT current source 12 and is stored in the external capacitor Cd, so that the voltage level of the output terminal XO is increased as indicated by dashed dotted lines of FIG. 13.
If the voltage level of the output terminal XO is increased, the current from the PTAT current source 12 flows toward the input terminal XI through the feedback resistor Rf (for example, a resistance value thereof is about 1MΩ). As a result, the external capacitor Cd is charged, so that the voltage level of the input terminal XI is increased as shown by the solid line of FIG. 13.
If the voltage level of the input terminal XI is increased from an initial state (about 0[V]) and then reaches the vicinity of a threshold voltage Vth of the NMOS transistor 44 included in the oscillating buffer 14, the oscillating buffer 14 is turned on, so that the voltage levels of the input terminal XI and the output terminal XO reach a bias level BIAS as shown in FIG. 13. From such a state, a signal of an oscillation frequency based on the crystal unit Xtal is amplified, so that the oscillator circuit starts to oscillate as shown in FIG. 13.
In the oscillator circuit 100 according to the related art, as shown in FIG. 13, the voltage level of the output terminal XO is increased by the current Iall flowing from the PTAT current source 12. Meanwhile, the increase in the voltage level of the input terminal XI is delayed by a time constant of the feedback resistor Rf and the external capacitor Cg. When the voltage level of the input terminal XI is equal to or less than a threshold voltage Vth of the NMOS transistor included in the oscillating buffer 14, the oscillating buffer 14 cannot operate. Thus, the current Iall from the PTAT current source 12 flows into the output terminal XO.
When a resistance value of the feedback resistor Rf is large, the increase in the voltage level of the input terminal XI is delayed because charging of the external capacitor Cg is delayed, so that the voltage level of the output terminal XO may be increased up to a level exceeding a breakdown voltage level Va of the PMOS transistor 42 and the NMOS transistor 44. As described above, if the voltage level of the output terminal XO exceeds the breakdown voltage level Va of the PMOS transistor 42 and the NMOS transistor 44, these transistors are broken and are always in a conductive state, so that an oscillation operation may be impossible. This problem becomes severe when the PMOS transistor 42 and the NMOS transistor 44 are formed by a core transistor having a breakdown voltage lower than that of an I/O transistor.